The present invention relates to phase shifting apparatus in general and more particularly to a symmetrical digital pulse shifter for controllably and symmetrically shifting in two opposite directions an inputted signal.
Digital delay lines are well known, which are used to introduce a phase delay between two signals, in particular between logic signals each having two opposite logical states as a function of time. For instance, U.S. Pat. No. 3,588,707 of R. A. Manship uses a tapped shift register to create a digital time delay of various length.
It is known from U.S. Pat. No. 3,760,280 of M. T. Covington to control the delay of an analog signal in response to a control signal by conversion through a voltage controlled oscillator into a binary signal which is frequency modulated, using a shift register as a delay line, which is actuated by a clock.
It is known from U.S. Pat. No. 3,833,854 of R. W. Schonover to count with a common clock the same number of pulses from two different count references in order to create a phase shift between two digital signals equal to the difference between the two count references.
An object of the present invention is to provide a phase shifter wherein digital technique is used to symmetrically shift two square-wave signals.
Another object of the present invention is to combine delay lines for generating symmetrical phase shifts between digital signals.
An object of the present invention is also to generate controlled symmetrical phase shifts in two digital signals relative to a common time reference by using variable length random access memory devices.